Sum with carrier bit

Clear[Op1,Op2,Op3,i,j,n,m];

CB=IdentityMatrix[2];
H=(1/(Sqrt[2])){{1,1},{1,-1}}; (*Hadamard gate*)

X=PauliMatrix[1];
Y=PauliMatrix[2];
Z=PauliMatrix[3];(*Phase-flip gate*)

controlledU[matrixU_?MatrixQ,control_?IntegerQ]:=MatrixPower[matrixU,CB[[control+1]][[2]]+2](*definition of a controlled U*)
bitconfig=Partition[Flatten[Table[{i-1,m-1,j-1,n-1},{i,1,2},{m,1,2},{j,1,2},{n,1,2}]],4];(*all 4 bit configurations*)
L=Length[bitconfig];

Op1[i_,m_,j_,n_]:=Flatten[TensorProduct[CB[[i]],CB[[m]],controlledU[(H.Z.H),(i-1)( m-1)].CB[[j]],CB[[n]]]]
Op2[i_,m_,j_,n_]:=Flatten[TensorProduct[CB[[i]],CB[[m]],CB[[j]],controlledU[(H.Z.H),(i-1)].CB[[n]]]]
Op3[i_,m_,j_,n_]:=Flatten[TensorProduct[CB[[i]],CB[[m]],CB[[j]],controlledU[(H.Z.H),(m-1)].CB[[n]]]]

A1=Partition[Flatten[Table[Op1[i,m,j,n],{i,1,2},{m,1,2},{j,1,2},{n,1,2}]],L];
A2=Partition[Flatten[Table[Op2[i,m,j,n],{i,1,2},{m,1,2},{j,1,2},{n,1,2}]],L];
A3=Partition[Flatten[Table[Op3[i,m,j,n],{i,1,2},{m,1,2},{j,1,2},{n,1,2}]],L];

multiTP[i_,m_,j_,n_]:=Flatten[TensorProduct[CB[[i+1]],CB[[m+1]],CB[[j+1]],CB[[n+1]]]]

Example 1

First two bits are input, third one is the carrier bit, last one is the sum mod 2

Input : [0100]

input= multiTP[0,1,0,0];

Output :

out=A3.A2.A1.input

Transpose[bitconfig].out

Example 2

Input : [1100]

input= multiTP[1,1,0,0];

Output :

out=A3.A2.A1.input

Transpose[bitconfig].out